Display device

ABSTRACT

A light shielding layer overlapping with a peripheral region of a display device includes extension portions each extending along a Y direction, bent portions located between the extension portions, and another extension portion located between the bent portions. In a region overlapping with the another extension portion, an enable line (first potential supply line), which supplies a potential to a plurality of scanning signal lines via a driving circuit (first driving circuit), goes through a wiring layer (first wiring layer) and another wiring layer (second wiring layer) made of a material having resistivity lower than that of the wiring layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese PatentApplications No. 2016-175373 filed on Sep. 8, 2016 and No. 2016-175374filed on Sep. 8, 2016, the contents of which are hereby incorporated byreference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a display device.

BACKGROUND OF THE INVENTION

A display device generally has a rectangular external shape. In recentyears, however, with expansion of fields of application of the displaydevice, there is also a display device having a shape other than arectangle. Such display device is disclosed, for example, in JapanesePatent Application Laid-Open Publication No. 2009-122636 (PatentDocument 1) and Japanese Patent Application Laid-Open Publication No.2008-292995 (Patent Document 2).

SUMMARY OF THE INVENTION

In a display region of a display device, there are a plurality ofelectrodes driving an electro-optical layer, and a signal line supplyinga driving signal and a scanning signal to the plurality of electrodes.In a peripheral region around the display region, a circuit supplying asignal to the above-described plurality of electrodes is disposed. In acase where a shape of the display region or a shape of an outer edgeportion of the peripheral region is a shape other than a rectangle or asquare, a problem may arise due to the shape of the display region orthe peripheral region. In the present specification, the shape otherthan the rectangle or the square may be referred to as an “irregularshape” hereinafter.

For example, in a case where each length of a plurality of signal linesis different from each other due to the display region having theirregular shape, in-plane distribution of a load given to each of thesignal lines becomes uneven. When the in-plane distribution of the loadgiven to each of the signal lines becomes uneven in this way, it maycause deterioration of image quality.

Also, when each of the plurality of signal lines is made to have thesame length, it is necessary to make an external shape of the peripheralregion a rectangle. In this case, an area occupied by the display regionin the display device is reduced.

An object of the present invention is to provide a technique forimproving performance of a display device.

The typical ones of the inventions disclosed in the present applicationwill be briefly described as follows.

A display device as one aspect of the present invention includes: adisplay region in which first pixels are arrayed; a peripheral regionoverlapping with a light shielding layer and being outside the displayregion; a plurality of scanning signal lines and a plurality of videosignal lines within the display region; a first driving circuit and asecond driving circuit supplying a scanning signal; a first potentialsupply line supplying a potential to the plurality of scanning signallines via the first driving circuit; and a first wiring layer and asecond wiring layer made of a material having resistivity lower thanthat of the first wiring layer. The plurality of video signal linesextend in a first direction. The light shielding layer includes a firstextension portion and a second extension portion each extending alongthe first direction, a first bent portion and a second bent portionlocated between the first extension portion and the second extensionportion, and a third extension portion located between the first bentportion and the second bent portion. The first extension portion isconnected to the first bent portion, and the second extension portion isconnected to the second bent portion. The first potential supply lineoverlaps with the third extension portion. The plurality of scanningsignal lines include a first scanning signal line and a second scanningsignal line. A part of the first scanning signal line overlaps with thethird extension portion, and a part of the second scanning signal lineoverlaps with the first extension portion. In plan view, the number ofthe plurality of video signal lines crossed by the first scanning signalline is different from the number of the plurality of video signal linescrossed by the second scanning signal line within the display region. Ina region overlapping with the third extension portion, the firstpotential supply line goes through the first wiring layer and the secondwiring layer.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a plan view illustrating one exemplary configuration of adisplay device according to one embodiment;

FIG. 2 is an enlarged cross-sectional view illustrating a part of adisplay region of the display device illustrated in FIG. 1;

FIG. 3 is a plan view illustrating an exemplary arrangement of a commonelectrode in the display device illustrated in FIG. 1;

FIG. 4 is an equivalent circuit diagram illustrating a pixel in thedisplay device illustrated in FIG. 1;

FIG. 5 is an enlarged cross-sectional view illustrating a connectingpart between a driver chip and a substrate illustrated. in FIG. 1;

FIG. 6 is a circuit block diagram illustrating an exemplaryconfiguration of a scanning signal line driving circuit illustrated inFIG. 1;

FIG. 7 is a circuit diagram schematically illustrating a factor of aload that is given to each of a plurality of pixels illustrated in FIG.3;

FIG. 8 is an enlarged plan view illustrating details of a circuitconfiguration of an upper side of the display device illustrated in FIG.3;

FIG. 9 is an enlarged plan view illustrating an exemplary layout ofwirings supplying a clock signal to a driving circuit in the same partas the display device illustrated in FIG. 8;

FIG. 10 is an enlarged plan view of a display device that is amodification of FIG. 8;

FIG. 11 is an enlarged plan view illustrating a circuit layout around acircuit block illustrated in FIG. 10;

FIG. 12 is an enlarged plan view illustrating a modification of FIG. 11;

FIG. 13 is an enlarged plan view of a display device that is anothermodification of FIG. 10;

FIG. 14 is an enlarged plan view illustrating a circuit layout around acircuit block illustrated in FIG. 13;

FIG. 15 is an enlarged plan view illustrating a circuit layout aroundanother circuit block different from the circuit block illustrated inFIG. 14, among a plurality of circuit blocks illustrated in FIG. 13;

FIG. 16 is an enlarged plan view illustrating a circuit layout around acircuit block of a display device that is a modification of FIGS. 12 and14;

FIG. 17 is an enlarged plan view illustrating details of a circuitconfiguration of a lower side of the display device illustrated in FIG.3;

FIG. 18 is an enlarged plan view illustrating an exemplary layout of acommon electrode on a plane illustrated in FIG. 17; and

FIG. 19 is a circuit block diagram illustrating a modification of thecircuit block illustrated in FIG. 6.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to the drawings.

Note that this disclosure is an example only and suitable modificationswhich can be easily conceived by those skilled in the art withoutdeparting from the gist of the present invention are included within thescope of the invention as a matter of course. In addition, in order tofurther clarify the description, a width, a thickness, a shape, and thelike of respective portions may be schematically illustrated in thedrawings as compared to aspects of the embodiments, but they areexamples only and do not limit the interpretation of the presentinvention.

In addition, in this specification and the respective drawings, the samecomponents described in the drawings which have been described beforeare denoted by the same reference characters, and detailed descriptionthereof may be omitted as needed.

Further, hatching which is applied in order to distinguish a structureis sometimes omitted in the drawings used in the embodiments dependingon the drawing.

Also, a technique described in an embodiment below is widely applicableto a display device provided with a mechanism in which a signal from aperiphery of a display region is supplied to a plurality of elements inthe display region provided with an electro-optical layer. Theelectro-optical layer is a layer provided with an element having afunction of forming a display image and being driven by an electriccontrol signal. Various display devices may be exemplified as theabove-described display device such as a liquid crystal display device,an organic electro-luminescence (EL) display device, and a plasmadisplay device, for example. In the embodiment below, the liquid crystaldisplay device is selected and described as a typical example of thedisplay device.

The liquid crystal display device is roughly classified into thefollowing two, depending on a direction of applying an electric fieldfor changing alignment of a liquid crystal molecule in a liquid crystallayer serving as a display functional layer. That is, as a firstcategory, there is a so-called vertical electric field mode in which theelectric field is applied in a thickness direction (or an out-of-planedirection) of the display device. In the vertical electric field mode,for example, there are a twisted nematic (TN) mode, a vertical alignment(VA) mode, and the like. As a second category, there is a so-calledhorizontal electric field mode in which the electric field is applied ina plane direction (or an in-plane direction) of the display device. Inthe horizontal electric field mode, for example, there are an in-planeswitching (IPS) mode, a fringe field switching (FFS) mode which is oneof the IPS modes, and the like. Although the technique described belowis applicable to any of the vertical electric field mode and thehorizontal electric field mode, a display device of the horizontalelectric field mode will be described in the embodiment below, by way ofexample.

<Configuration of Display Device>

FIG. 1 is a plan view illustrating one exemplary configuration of adisplay device according to one embodiment. FIG. 2 is an enlargedcross-sectional view illustrating a part of a display region of thedisplay device illustrated in FIG. 1. FIG. 3 is a plan view illustratingan exemplary circuit layout in the display device illustrated in FIG. 1.FIG. 4 is an equivalent circuit diagram illustrating a pixel in thedisplay device illustrated in FIG. 3. FIG. 5 is an enlargedcross-sectional view illustrating a connecting part between a driverchip and a substrate illustrated in FIG. 1. FIG. 6 is a circuit blockdiagram illustrating an exemplary configuration of a scanning signalline driving circuit illustrated in FIG. 1. Note that, in FIG. 1, a partof a peripheral region SA overlapping with a light shielding layer BM isindicated with a pattern having a darker color than that of a displayregion DA. Also, in FIG. 2, to illustrate an exemplary positionalrelation between a scanning signal line GL and a video signal line SL ina thickness direction of a substrate SUB1, the scanning signal line GL,which is provided to a cross-section different from FIG. 2, is alsoillustrated. Also, to a switching circuit SWS illustrated in FIG. 3, alarge number of video signal connecting lines SCL are connected, and inFIG. 3, a region in which a large number of video signal connectinglines SCLs are arranged is indicated with a dotted pattern.

As illustrated in FIG. 1, a display device DSP1 includes a display panelPNL1 and a driver chip DRC1 mounted on the display panel PNL1. Thedisplay panel PNL1 has a display surface DS (see FIG. 2) on which animage is displayed. The driver chip DRC1 is an integrated circuit (IC)chip provided with a control circuit for controlling driving of thedisplay panel PNL1. The display device DSP1 also includes a wiring board(wiring portion) FWB1, which is a wiring member connected to the displaypanel PNL1. The wiring board FWB1 is a flexible wiring board having aplurality of wirings covered with resin. The wiring board FWB1 isconnected to a terminal portion TM1 of the display panel PNL1 asschematically illustrated with an arrow in FIG. 1. To the terminalportion TM1, not only an electric signal such as a driving signal and avideo signal but also a power supply voltage for driving the displaypanel PNL1 is supplied from an external circuit of the display panelPNL1 via the wiring board FWB1.

Also, the display panel PNL1 is provided with the display region DA, inwhich a plurality of pixels (first pixels) PX (see FIG. 3) are arrayed,and the peripheral region SA outside the display region DA. In theexample illustrated in FIG. 1, the display region DA is trapezoidal, anda long side and a short side extending in parallel to each other extendalong a Y direction. Also, in the example illustrated in FIG. 1, the Ydirection is a longer direction of the display region DA. The displayregion DA is a region in which an image visible from a display surfaceDS (see FIG. 2) side is displayed based on a signal input into thedisplay device DSP1. In plan view, the peripheral region SA is disposedso as to continuously surround a periphery of the display region DA. Inplan view, a side (end) on an inner side of the peripheral region SA isin contact with an outer edge portion of the display region DA. In thedisplay region DA, the plurality of pixels PX are arrayed. For example,as illustrated in FIG. 3, in plan view, two directions crossing eachother, preferably orthogonal to each other, are referred to as an Xdirection and a Y direction. In plan view, the plurality of pixels PXare arrayed in the X direction and the Y direction in a matrix withinthe display region DA. Note that, in the present application, “in planview” means a view viewed from a direction perpendicular to the displaysurface of the display panel PNL1.

Also, the peripheral region SA is a non-display region in which theimage, which is visible from outside, is not displayed and is disposedso as to surround the periphery of the display region DA. The peripheralregion SA is the non-display region, and most of the peripheral regionSA overlaps with the light shielding layer BM.

Also, as illustrated in FIG. 2, the display panel PNL1 includes thesubstrate SUB1, a substrate SUB2 disposed facing the substrate SUB1, anda liquid crystal layer LQ serving as an electro-optical layer disposedbetween the substrate SUB1 and the substrate SUB2. In other words, thedisplay device DSP1 according to this embodiment is a liquid crystaldisplay device provided with the liquid crystal layer LQ serving as theelectro-optical layer. In other words, note that the substrate SUB1 isan array substrate, and the substrate SUB2 is a counter substrate inthis embodiment.

As illustrated in FIG. 1, the driver chip DRC1 and the terminal portionTM1 are in a region (exposed region) NDA2 not overlapping with the lightshielding layer BM, of the peripheral region SA of the display panelPNL1. When one side in the Y direction illustrated in FIG. 1 is referredto as a Y1 side and the other side therein is referred to as a Y2 side,the region NDA2 is on the Y1 side of the display region DA in the Ydirection. As illustrated in FIG. 2, in the display panel PNL1, thesubstrate SUB1 and the substrate SUB2 face each other in the most partin plan view. However, the region NDA2 illustrated in FIG. 1 is exposedfrom the substrate SUB2 (see FIG. 5). In an example illustrated in FIG.5, the light shielding layer BM is formed in the substrate SUB2, and theregion NDA2 (see FIG. 1) does not overlap with the light shielding layerBM. Note that the light shielding layer BM is also disposed within thedisplay region DA in addition to the peripheral region SA. In plan view,the right shielding layer BM is provided so as to surround a peripheryof each of the plurality of pixels PX in the display region DA (see FIG.3).

The driver chip DRC1 is mounted in a region DRA in the peripheral regionSA (more specifically, the region NDA2). As illustrated in FIG. 5, inthe region DRA of the substrate SUB1, a terminal PD1 and a terminal PD2are disposed, and the driver chip DRC1 is connected to the terminal PD1and the terminal PD2. The terminal PD1 is an interface electricallyconnecting a circuit formed in the driver chip DRC1 to a circuit formedin the display panel PNL1 (see FIG. 1). Also, the terminal PD2 is aninterface electrically connecting the driver chip DRC1 with the wiringboard FWB1. The driver chip DRC1 is connected with a terminal PD3 viathe terminal PD2 and a wiring FDW. Also, to the terminal PD3, a wiringFW of the wiring board FWB1 is connected. Also, as illustrated in FIG.1, at least a part of the driver chip DRC1 (for example, a long side)extends along a direction T3 that is inclined relative to each of the Ydirection and the X direction.

As illustrated in FIG. 4, the display device DSP1 has a video signalline driving circuit SD. The video signal line driving circuit SD iselectrically connected to a pixel PX to drive the liquid crystal layerLQ serving as the electro-optical layer via the video signal line SL. Inthe example of this embodiment, the video signal line driving circuit SDformed in the driver chip DRC1. The video signal line driving circuit SDsupplies a video signal Spic to a pixel electrode (first electrode) PEprovided to each of the plurality of pixels PX via the video signal lineSL. Also, as illustrated in FIG. 6, the driver chip DRC1 includes acontrol circuit (first control circuit) CTC supplying a control signalto a driving circuit via a control wiring GW. The control circuit CTC iselectrically connected to the driving circuit via the terminal PD1 (seeFIG. 5).

In this embodiment, as illustrated in FIG. 5, there is described anexample in which the driver chip DRC1 is mounted on the substrate SUB1.Note that there are various modifications of a position of the driverchip DRC1 and a position of the control circuit CTC besides those in theregion DRA illustrated in FIG. 1. For example, the driver chip DRC1 mayalso be mounted on the wiring board FWB1. In such case, the wiring boardFWB1 is connected to the terminal PD1. Accordingly, even in a case wherethe driver chip DRC1 is mounted on the wiring board FWB1, the controlcircuit CTC of the driver chip DRC1 is electrically connected to thedriving circuit via the terminal PD1 in the region DRA.

As illustrated in FIG. 3, the display device DSP1 includes a pluralityof video signal lines SL and a plurality of pixels PX. In the displayregion DA, the plurality of pixels PX are arranged between the substrateSUB1 and the substrate SUB2 (see FIG. 2). The plurality of pixels PX arearrayed in the X direction and the Y direction in a matrix and arrangedm by n (when m and n are positive integers). Each of the plurality ofvideo signal lines SL extends in the Y direction and is arrayed in the Xdirection at an interval from each other. Each of the plurality ofpixels PX is partitioned by the video signal lines SL in the Xdirection. Accordingly, the number of the pixels PX arrayed along the Xdirection corresponds to the number of the video signal lines SL. In theexample illustrated in FIG. 3, m video signal lines SL are arrayed in anorder of video signal lines SL1, SL2, and SLm, from X1 which is one sidein the X direction, toward X2 which is the other side therein. Each ofthe plurality of video signal lines SL is drawn out to the peripheralregion SA outside the display region DA. Each of the plurality of videosignal lines SL is electrically connected with the driver chip DRC1 viathe video signal connecting lines SCL as connecting wirings (alsoreferred to as lead-out wirings) interconnecting the video signal linesSL within the display region DA and the driver chip DRC1.

The video signal lines SL and the video signal connecting lines SCL arevideo lines functioning as wirings transmitting a video signal, and thevideo signal lines SL and the video signal connecting lines SCL can bedistinguished from each other as follows. That is, of the video lineserving as a signal transmission path connected to the driver chip DRC1and supplying the video signal to the plurality of pixels PX, a part(wiring portion) thereof in a position overlapping with the displayregion DA is referred to as the video signal lines SL. A part (wiringportion) of the above-described video lines outside the display regionDA is referred to as the video signal connecting lines SCL (or as alead-out wiring). Each of the plurality of video signal lines SL extendslinearly in the Y direction. In contrast, since the video signalconnecting lines SCL are the wirings connecting the video signal linesSL and the driver chip DRC1, as illustrated in FIG. 3, the video signalconnecting lines SCL have bent portions between the video signal linesSL and the driver chip DRC1.

In the example illustrated in FIG. 3, there is a switching circuit(selection circuit) SWS between the video signal lines SL and the videosignal connecting lines SCL. The switching circuit SWS is a multiplexercircuit constituted by a plurality of transistors, for example, andoutputs a signal that has been input by selecting from the video signalline SL for each color. The switching circuit SWS operates as aselection switch selecting a type of the video signal such as a redsignal, a green signal, or a blue signal, for example. In other words,the switching circuit SWS is a selection circuit selecting a type of thevideo signal Spic (see FIG. 4) supplied to the video signal lines SL. Inthis case, the number of the video signal connecting lines SCLconnecting the switching circuit SWS and the driver chip DRC1 is smallerthan the number of the video signal lines SL. In this way, by providingthe switching circuit SWS, it is possible to reduce the number of thevideo signal connecting lines SCL, whereby it is possible to reduce thenumber of the video signal connecting lines SCL between the driver chipDRC1 and the switching circuit SWS. In a case where the switchingcircuit SWS is provided as illustrated in FIG. 3, it is possible todistinguish between the video signal lines SL and the video signalconnecting lines SCL as follows. That is, a part (wiring portion)connecting the driver chip DRC1 and the switching circuit SWS isreferred to as the video signal connecting lines SCL. Also, from a part(wiring portion) of the video line in a position overlapping with thedisplay region DA to a part (wiring portion) thereof connected to theswitching circuit SWS is referred to as the video signal lines SL.

Also, as illustrated in FIG. 3, the switching circuit SWS is curvedconforming to a shape of a side on the Y1 side of the display region DA.More specifically, since the switching circuit SWS is constituted by theplurality of transistors, an array line of the plurality of transistorsconstituting the switching circuit SWS is curved along the shape of theside on the Y1 side of the display region DA. Since the switchingcircuit SWS is curved along the side on the Y1 side of the displayregion DA in this way, of the peripheral region SA, it is possible toreduce an area of a part on the Y1 side (bent portions BEN3 and BEN4 anextension portion EXT4 illustrated in FIG. 1).

Also, the display device DSP1 includes a plurality of scanning signallines GL, and a driving circuit GD as a scanning signal output circuitoutputting a scanning signal Gsi input into the plurality of scanningsignal lines GL (see FIG. 6). The driving circuit is provided on thesubstrate SUB1 in the peripheral region SA (see FIG. 1). The driver chipDRC1 is connected to the driving circuit via the control wiring GW. Eachof the plurality of scanning signal lines GL extends in the X directionand is arrayed in the Y direction at an interval from each other. Eachof the plurality of pixels PX is partitioned by each of the scanningsignal lines GL in the Y direction. Accordingly, the number of thepixels PX arrayed along the Y direction corresponds to the number of thescanning signal lines GL. In the example illustrated in FIG. 3, nscanning signal lines GL are arrayed in an order of scanning signallines GL1, GL2, and GLn from one side to the other side in the Ydirection. Each of the plurality of scanning signal lines GL is drawnout to the peripheral region SA outside the display region DA and isconnected to the driving circuit. Also, the plurality of scanning signallines GL mutually cross the plurality of video signal lines SL. Thescanning signal line GL includes a gate electrode GE of a transistor(pixel transistor) Tr1 serving as a pixel switch element PSW illustratedin FIG. 4.

In FIG. 3, a region in which the driving circuit GD is provided isschematically illustrated being surrounded with a frame. The drivingcircuit includes multiple types of circuit portions. For example, asillustrated in FIG. 6, the driving circuit GD includes a shift registercircuit GSR, and a switching circuit (scanning signal switching circuit)GSW connected to the shift register circuit GSR and selecting apotential to be supplied to the scanning signal line GL based on acontrol signal. Also, the driving circuit GD is connected to the driverchip DRC1 via the control wiring GW. The driver chip DRC1 supplies acontrol signal such as a clock signal GCL and an enable signal ENB tothe driving circuit GD via the control wiring GW.

In the example illustrated in FIG. 6, the clock signal GCL istransmitted to each of a plurality of shift register circuits GSR of thedriving circuit GD via a clock line GWC. The enable signal ENB istransmitted to each of the plurality of switching circuits GSW of thedriving circuit GD via an enable line GWE. The enable line GWE is apotential supply line supplying the potential as the scanning signal Gsito the scanning signal line GL. In the example illustrated in FIG. 6, ascanning signal Gsi1 is supplied to the scanning signal line GL1, ascanning signal Gsi2 is supplied to the scanning signal line GL2, and ascanning signal Gsin is supplied to the scanning signal line GLn. Asschematically illustrated in FIG. 6, each of the plurality of scanningsignals Gsi is a pulse signal having a voltage level that changescorresponding to a timing of the clock signal GCL. A start pulse signalGSP is transmitted to the shift register circuit GSR that is drivenfirst among the plurality of shift register circuits GSR via a startpulse line GWS.

In the example illustrated in FIG. 6, a set of the shift registercircuit GSR and the switching circuit GSW constitutes a circuit blockGDB1 or GDB2, and each of the circuit blocks GDB1 and GDB2 is connectedto the scanning signal line GL. In FIG. 6, for easy understanding, oneswitching circuit GSW is connected to one shift register circuit GSR,and the scanning signal line GL is connected to each of the switchingcircuits GSW. However, there are various modifications of a circuitconfiguration of the circuit blocks GDB1 and GDB2. For example, it isalso possible to connect the plurality of switching circuits GSW to oneshift register circuit GSR.

Furthermore, a buffer circuit GBU is connected between the drivingcircuit GD and the driver chip DRC1. The buffer circuit GBU is a circuitrelaying the potential to be supplied to the scanning signal line GL viathe driving circuit GD. In a case where the buffer circuit GBU isinterposed in a transmission path of the control signal, a waveform of agate signal supplied to the driving circuit GD is corrected by thebuffer circuit GBU. As illustrated in FIG. 6, the buffer circuit GBU anda power supply circuit PSC are connected to each other via a powersupply wiring PL supplying a power supply potential to the drivingcircuit GD. More specifically, the buffer circuit GBU and the powersupply circuit PSC are connected to each other via a wiring PLH in whicha relatively high potential VDH is supplied and a wiring PLL in which apotential lower than the potential VDH is supplied. In the buffercircuit GBU, by using the potential VDH and a potential VDL, a waveformof the control signal such as the enable signal ENB is corrected and isoutput to the driving circuit GD. The power supply circuit PSCillustrated in FIG. 6 is formed in the wiring board FWB1, for example.As a modification, the power supply circuit PSC may also be formedoutside the display device DSP1 and may be connected to the buffercircuit GBU through the wiring board FWB1.

In the example illustrated in FIG. 3, the driving circuit GD is disposedboth on an X1 side which is one side, and an X2 side which is the otherside, in the X direction. More specifically, in the X direction, thereare a driving circuit (scanning signal line driving circuit, firstdriving circuit) GD1 on the X1 side and a driving circuit (scanningsignal line driving circuit, second driving circuit) GD2 on the X2 side.Also, in the X direction, the display region DA is a region between thedriving circuit GD1 and the driving circuit GD2. As illustrated in FIG.3, a driving method in a state where the driving circuit GD is connectedto both ends of the scanning signal lines GL is referred to as aboth-side driving method of the scanning signal lines GL. Note thatthere are various modifications of a layout of the driving circuit GD.For example, in the X direction illustrated in FIG. 3, the drivingcircuit GD may also be disposed on any one of the X1 side and the X2side. A driving method in a state where the driving circuit GD isconnected to one end of the scanning signal lines GL while the drivingcircuit GD is not connected to the other end thereof is referred to as aone-side driving method of the scanning signal line GL. Also, forexample, it is also possible that no buffer circuit GBU (see FIG. 6) isconnected between the driver chip DRC1 and the driving circuit GD.

Also, as illustrated in FIG. 2, the display device DSP1 includes acommon electrode (second electrode) CE. Also, as illustrated in FIG. 4,the display device DSP1 includes a common electrode driving circuit(also referred to as a common potential circuit) CD driving the commonelectrode CE when the display device DSP1 displays an image. The commonelectrode CE is electrically connected to the common electrode drivingcircuit CD via a common line CML. In the example illustrated in FIG. 4,the common electrode driving circuit CD is formed in the wiring boardFWB1. The common electrode CE is an electrode in which a potentialcommon to each of the plurality of pixels is supplied. Accordingly, onecommon electrode CE may be provided so as to overlap with the displayregion DA. Note that it is also possible to provide the common electrodeCE that is divided into a plurality of electrodes so as to overlap withthe display region DA.

Note that there are various modifications of a position where the commonelectrode driving circuit CD is formed in addition to an aspectillustrated in FIG. 3. For example, the common electrode driving circuitCD may be formed in the driver chip DRC1. Furthermore, for example, anembodiment in which the common electrode driving circuit CD is disposedon the substrate SUB1 illustrated in FIG. 1 is also included in theaspect in which the common electrode driving circuit CD is formed in theperipheral region SA. It is also possible that, for example, the commonelectrode driving circuit CD is formed outside the display device DSP1and is connected to the wiring board FWB1.

As illustrated in FIG. 4, the pixel PX includes the pixel switch elementPSW, and a pixel electrode PE. Also, in the example of this embodiment,the plurality of pixels PE share the common electrode CE. The pixelswitch element PSW includes, for example, the transistor Tr1 that is athin film transistor (TFT). The pixel switch element PSW is electricallyconnected to the scanning signal line GL and the video signal line SL.More specifically, a source electrode SE of the transistor Tr1 servingas the pixel switch element PSW is connected to the video signal linesSL, and a drain electrode DE thereof is connected to the pixel electrodePE. Also, the gate electrode GE of the transistor Tr1 is included in thescanning signal line GL. The driving circuit (see FIG. 3) supplies thepotential (scanning signal Gsi illustrated in FIG. 6) to the gateelectrode GE and controls a state of supply of the video signal Spic tothe pixel electrode PE by on-off operating the pixel switch element PSW.In other words, the transistor Tr1 functions as the pixel switch elementPSW controlling supply of the potential to the pixel electrode PE. Thepixel switch element PSW may be either of a top gate type TFT or abottom gate type TFT. Also, a material of a semiconductor layer of thepixel switch element PSW is olycrystalline silicon (polysilicon), forexample; however, it may also be an oxide semiconductor or amorphoussilicon.

The pixel electrode PE is opposed to the common electrode CE interposingan insulating film 14 (see FIG. 2). The common electrode CE, theinsulating film 14, and the pixel electrode PE form a holding capacitorCS. During a display operation period in which a display image is formedbased on a video signal, an electric field is formed between the pixelelectrode PE and the common electrode CE based on a driving signalapplied to each of the electrodes. Then, a liquid crystal moleculeconstituting the liquid crystal layer LQ, which is the electro-opticallayer, is driven by the electric field formed between the pixelelectrode PE and the common electrode CE. For example, in the displaydevice DSP1 using the horizontal electric field mode as in thisembodiment, the pixel electrode PE and the common electrode CE areprovided in the substrate SUB1 as illustrated in FIG. 2. The liquidcrystal molecule constituting the liquid crystal layer LQ is rotatedusing the electric field (for example, in a fringe field, an electricfield that is substantially in parallel to a principal surface of asubstrate) formed between the pixel electrode PE and the commonelectrode CE.

That is, during the display operation period, each of the pixelelectrode PE and the common electrode CE operates as a driving electrodedriving the liquid crystal layer LQ, which is the electro-optical layer.In other words, each of the plurality of pixel electrodes PE is thefirst electrode driving the electro-optical layer. Furthermore, each ofthe common electrodes CE is the second electrode driving theelectro-optical layer.

As illustrated in FIG. 2, the substrate SUB1 and the substrate SUB2 arebonded together in a state of being separated from each other. Theliquid crystal layer LQ is sealed between the substrate SUB1 and thesubstrate SUB2. The substrate SUB1 includes an insulating substrate 10having optical transparency, for example, a glass substrate and a resinsubstrate. Also, the substrate SUB1 has a plurality of conductorpatterns on the insulating substrate 10 on a side thereof facing thesubstrate SUB2. The plurality of conductor patterns include theplurality of scanning signal lines GL, the plurality of video signallines SL, a plurality of common lines CML, the plurality of commonelectrodes CE, and the plurality of pixel electrodes PE. Also, aninsulating film is interposed between the conductor patterns. As theinsulating films disposed between the adjacent conductor patterns andinsulating the conductor patterns from each other, there are included aninsulating film 11, an insulating film 12, an insulating film 13, aninsulating film 14, and an alignment film AL1. Note that, in FIG. 2, oneeach of the scanning signal lines GL, the common electrodes CE, and thecommon lines CML is illustrated.

Each of the plurality of conductor patterns described above is formed ina plurality of wiring layers that are layered. In the exampleillustrated in FIG. 2, each of the common electrode CE and the pixelelectrodes PE is formed in a different layer, and below the layer inwhich the common electrode CE is formed, three wiring layers areprovided. In a wiring layer WL1 of a first layer that is provided theclosest to the insulating substrate 10 among the three wiring layersformed over the insulating substrate 10, mainly the scanning signal lineGL is formed. The conductor pattern formed in the wiring layer WL1 ismade of, for example, metal such as chrome (Cr), titanium (Ti), andmolybdenum (Mo), or an alloy thereof.

The insulating film 11 is formed over the wiring layer WL1 and theinsulating substrate 10. The insulating film 11 is a transparentinsulating film made of, for example, silicon nitride, silicon oxide, orthe like. Note that, between the insulating substrate 10 and theinsulating film 11, there are formed the gate electrode of the pixelswitch element, the semiconductor layer, and the like in addition to thescanning signal line GL.

Over the insulating film 11, a wiring layer WL2 of a second layer isformed. In the wiring layer WL2, mainly the video signal lines SL areformed. The wiring layer (second wiring layer) WL2 is made of a materialhaving lower resistivity than that of the wiring layer (first wiringlayer) WL1. The conductor pattern formed in the wiring layer WL2 is madeof a metal film having a multilayer structure, for example, in whichaluminum (Al) is sandwiched with molybdenum (Mo), titanium (Ti), or thelike. It is preferred that a wiring material of the wiring layer WL2have a lower specific resistance than that of a wiring material of thewiring layer WL1. Also, the source electrode, the drain electrode, andthe like of the pixel switch element are formed over the insulating film11. In the example illustrated in in FIG. 2, the video signal lines SLextend in the Y direction. The insulating film 12 is formed over each ofthe video signal lines SL and the insulating film 11. The insulatingfilm 12 is made of, for example, acrylic photosensitive resin.

Also, in the example illustrated in FIG. 2, over the insulating film 12,a wiring layer WL3 of a third layer is formed. In the wiring layer WL3,mainly the common line CML is formed. The conductor pattern formed inthe wiring layer WL3, in the same way as in the wiring layer WL2, ismade of a metal film having a multilayer structure, for example, inwhich aluminum (Al) is sandwiched with molybdenum (Mo), titanium (Ti),or the like. In the example illustrated in FIG. 2, the common line CMLextends in the Y direction. The insulating film 13 is formed over eachof the common line CML and the insulating film 12. The insulating film13 is made of, for example, acrylic photosensitive resin. Note that, inFIG. 2, an example is illustrated in which wirings such as the scanningsignal line GL, the video signal Lines SL, and the common line CML aredisposed in the three wiring layers, respectively. However, the numberof the wiring layers is not limited to the above, and variousmodifications are possible. For example, it is possible not to providethe wiring layer WL3 illustrated in FIG. 2. In this case, the commonline CML may be formed in the same layer as the layer in which thecommon electrode CE is formed, for example.

In FIG. 2, an enlarged cross-section of the display region DAillustrated in FIG. 1 is illustrated, and each of the wiring layers WL1,WL2, and WL3 illustrated in FIG. 2 is also disposed in the peripheralregion SA illustrated in FIG. 1. The video signal connecting lines SCL,the control wiring GW, and the power supply wiring PL illustrated inFIG. 3 are formed in one or more wiring layers of the wiring layers WL1,WL2, and WL3. Furthermore, each of a plurality of circuits disposed inthe peripheral region SA, such as the switching circuit SWS illustratedin FIG. 3, is formed in one or more wiring layers of the wiring layersWL1, WL2, and WL3.

As illustrated in FIG. 2, the common electrode CE is formed over theinsulating film 13. It is preferred that the common electrode CE be madeof a transparent conductive material such as indium tin oxide (ITO) orindium zinc oxide (IZO). Note that, in a case where the display deviceis a display device in the TN mode, the VA mode, or the like, which isthe vertical electric field mode, the common electrode CE may also beformed in the substrate SUB2. Also, in the cross-section illustrated inFIG. 2, the insulating film 13 is interposed between the commonelectrode CE and the common line CML. Note that a part of the commonline CML and a part of the common electrode CE are electricallyconnected to each other as illustrated in FIG. 4. In a case of areflection type display device using reflection of light from theoutside, the common electrode CE may also be made of a metal material.

The insulating film 14 is formed over the insulating film 13 and thecommon electrode CE. The pixel electrodes PE are formed over theinsulating film 14. In plan view, each of the pixel electrodes PE ispositioned between two adjacent video signal lines SL and is arranged ina position facing the common electrode CE. It is preferred that thepixel electrodes PE be made of a transparent conductive material such asITO and IZO or a metal material, for example. The alignment film AL1covers the pixel electrodes PE and the insulating film 14.

Meanwhile, the substrate SUB2 includes an insulating substrate 20 havingoptical transparency such as a glass substrate and a resin substrate.The substrate SUB2 also includes, over the insulating substrate 20 on aside thereof facing the substrate SUB1, the light shielding layer BMthat is a light shielding film, color filters CFR, CFG and CFB, anovercoating layer OCL, an alignment film AL2, and a conductive film CDF.

The conductive film CDF is disposed on a surface opposite to a surfacefacing the liquid crystal layer LQ among planes of the insulatingsubstrate 20. The conductive film CDF, for example, is made of atransparent conductive material such as ITO or IZO. The conductive filmCDF functions as a shield layer preventing an electromagnetic wave fromthe outside from affecting the liquid crystal layer LQ and the like.Also, in a case where a method of driving the liquid crystal layer LQ isthe vertical electric field mode such as the TN mode and the VA mode, anelectrode is provided to the substrate SUB2. This electrode alsofunctions as a shield layer, whereby it is possible to omit theconductive film CDF.

The display device DSP1 includes an optical element OD1 and an opticalelement OD2. The optical element OD1 is disposed between the insulatingsubstrate 10 and a backlight unit BL. The optical element OD2 isdisposed above the insulating substrate 20, that is, disposed on anopposite side of the substrate SUB1 interposing the insulating substrate20. Each of the optical element OD1 and the optical element OD2 includesat least a polarizer and may also include a wave plate as necessary.

<Planar Shape of Display Device and Circuit Layout>

Next, a relation between a planar shape of the display device and acircuit layout according to this embodiment will be described. FIG. 7 isa circuit diagram schematically illustrating a factor of a load that isgiven to each of a plurality of pixels illustrated in FIG. 3. Also, FIG.8 is an enlarged plan view illustrating details of a circuitconfiguration of an upper side of the display device illustrated in FIG.3.

Note that, in FIG. 7, to explicitly illustrate that the common electrodeCE is disposed across the plurality of pixels PX, a sheet-like commonelectrode CE is illustrated. Also, in FIG. 8, to make the circuit layoutof the driving circuits GD1 and GD2 easy to see, among the plurality ofcontrol wirings GW illustrated in FIG. 6, the enable line GWEtransmitting an enable signal is representatively illustrated. Also, inFIG. 8, the circuit blocks GDB1 and GDB2 illustrated in FIG. 6 areindicated with rectangles. Each of the circuit blocks GBA1, GBB1, GBC1,GBD1, and GBE1 illustrated in FIG. 8 is included in a plurality ofcircuit blocks GDB1 constituting the driving circuit GD1. Further, eachof the circuit blocks GBA2, GBB2, GBC2, GBD2, and GBE2 is included in aplurality of circuit blocks GDB2 constituting the driving circuit GD2.The circuit blocks GBA1, and GBA2, GBB1 and GBB2, GBC1 and GBC2, GBD1and GBD2, and GBE1 and GBE2 are respectively connected to the samescanning signal lines GL. In FIG. 8, for viewability, each of theplurality of scanning signal lines GL is indicated with an alternatelong and short dash line, and each of the plurality of video signallines SL is indicated with a dotted line. Also, in FIG. 8, in each ofthe enable lines GWE1 and GWE2, a part formed in the wiring layer WL1illustrated in FIG. 2 is indicated with a solid line, and a part formedin the wiring layer WL2 or the wiring layer WL3 is indicated with adotted line. Also, in FIG. 8, among the plurality of pixels PX, onepixel PXA connected to a scanning signal line GLA and one pixel PXEconnected to a scanning signal line GLE are schematically indicated withrectangles.

As illustrated in FIG. 1, in the display device DSP1 according to thisembodiment, a planar shape of the display region DA and an externalshape of the peripheral region SA are “irregular shapes.” In the exampleillustrated in FIG. 1, the display device DSP1 is also used as arearview mirror of a vehicle for checking rearward, and the planar shapeof the display region DA and the external shape of the peripheral regionSA are trapezoids. Also, in plan view, a shape of the light shieldinglayer BM disposed in the periphery of the display region DA is asfollows. That is, the light shielding layer BM includes an extensionportion (first extension portion) EXT1 and an extension portion (secondextension portion) EXT2 each extending along the Y direction. Also, thelight shielding layer BM has a bent portion (first bent portion) BEN1and a bent portion (second bent portion) BEN2 between the extensionportion EXT1 and the extension portion EXT2. Also, the extension portionEXT1 is connected to the bent portion BEN1, and the extension portionEXT2 is connected to the bent portion BEN2. Also, a length of theextension portion EXT2 is longer than a length of the extension portionEXT1. Also, in the example illustrated in FIG. 1, the light shieldinglayer BM has an extension portion (third extension portion) EXT3 betweenthe bent portion BEN1 and the bent portion BEN2. The extension portionEXT3 has a side (inner edge side) extending along a direction T1 whichis inclined relative to each of the Y direction and the X direction.Note that the direction which is inclined relative to the Y directionmeans a direction forming an angle other than a right angle or not inparallel to the Y direction. In the same way, the direction which isinclined relative to the X direction means a direction forming an angleother than the right angle or not in parallel to the X direction.

Note that the bent portion means a part where an extension directionchanges. The bent portion includes a part where it is curved in arounded manner in addition to a part where it is bent as illustrated inFIG. 1. In a case where it is curved in a rounded manner, a changeamount, (angle) of the extension direction of the curved part/totallength of the curved part may be defined as a curvature.

Also, in the example illustrated in FIG. 1, the light shielding layer BMhas the bent portion (third bent portion) BEN3 opposite to the bentportion BEN1 interposing the extension portion EXT1. Also, the lightshielding layer BM has the bent portion (fourth bent portion) BEN4opposite to the bent portion BEN2 interposing the extension portionEXT2. Also, the light shielding layer BM has the extension portion(fourth extension portion) EXT4 between the bent portion BEN3 and thebent portion BEN4, and the extension portion EXT4 has a side (inner edgeside) extending along a direction T2 which is inclined relative to eachof the Y direction and the X direction. In the example of thisembodiment, the display region DA constitutes a trapezoid, whereby thedirection T1 and the direction T2 are not in parallel to each other.Also, in the example illustrated in FIG. 1, the direction T2 and thedirection T3 are in parallel to each other. The description “thedirection T2 and the direction T3 are in parallel to each other”includes a case in which these directions are strictly in parallel inaddition to a case in which, even though these directions are notstrictly in parallel due to an influence of processing accuracy and thelike, they are regarded as being substantially in parallel to eachother. Note that, in FIG. 1, the bent portion BEN3 is described as thethird bent portion and the bent portion BEN4 is described as the fourthbent portion so as to distinguish them from the bent portion BEN1 andthe bent portion BEN2 on the Y2 side in the Y direction. Note that, asillustrated in FIG. 17 described below, focusing on the part on the Y1side, it is possible to reword the bent portion BEN3 as the first bentportion and the bent portion BEN4 as the second bent portion. In thesame way, the extension portion EXT4 is described as the fourthextension portion; however, it is also possible to reword it as thethird extension portion.

From a viewpoint of improving quality of an image displayed on thedisplay device DSP1, it is preferred that a value of a load (forexample, an impedance value caused by parasitic capacitance, wiringresistance, and the like) given to each of the plurality of pixels PXarrayed in the display region DA be made even within a plane overlappingwith the display region DA. Within the display region DA, when anin-plane distribution of the value of the load on the pixels PX becomesuneven, it may cause deterioration of image quality such as displayunevenness.

A load factor given to each of the plurality of pixels PX includes aparasitic capacitance C1 to a parasitic capacitance C5 as well as wiringresistance of each of the scanning signal lines GL and wiring resistanceof each of the video signal lines SL illustrated in FIG. 7. Theparasitic capacitance C1 is parasitic capacitance between the scanningsignal line GL and the video signal line SL. The parasitic capacitanceC2 is parasitic capacitance between a source electrode and a drainelectrode of the transistor Tr1, and the video signal line SL. Theparasitic capacitance C3 is parasitic capacitance between the sourceelectrode and the drain electrode of the transistor Tr1, and thescanning signal line GL. Also, the parasitic capacitance C4 is parasiticcapacitance between the scanning signal line GL and the common electrodeCE. The parasitic capacitance C5 is parasitic capacitance between thevideo signal line SL and the common electrode CE.

First, among the load factors given to each of the plurality of pixelsPX, consideration is made by focusing mainly on a load caused by thewiring resistance of the scanning signal lines GL. As illustrated inFIG. 8, each of the plurality of scanning signal lines GL is disposed soas to traverse the display region DA along the X direction. In a casewhere a shape of the display region DA is not a square or a rectangle,some of the plurality of scanning signal lines GL may have a differentlength (extending distance). For example, in The example illustrated inFIG. 8, the scanning signal line GLA and the scanning signal line GLEdiffer from each other in length. Specifically, the scanning signal lineGLA is connected to the circuit block GBA1 overlapping with theextension portion EXT3 and to the circuit block GBA2 overlapping withthe bent portion BEN2. In other words, a part of the scanning signalline GLA overlaps with the extension portion EXT3, and the other partthereof overlaps with the bent portion BEN2. Also, the scanning signalline GLE is connected to the circuit block GBE1 overlapping with theextension portion EXT1 and to the circuit block GBE2 overlapping withthe extension portion EXT2. In other words, a part of the scanningsignal line GLE overlaps with the extension portion EXT1, and the otherpart thereof overlaps with the extension portion EXT2. In this case, alength (extending distance) of the scanning signal line GLE is longerthan a length of the scanning signal line GLA.

Here, among the loads given to the pixel PXA located near the center ofthe scanning signal line GLA and the pixel PXE located near the centerof the scanning signal line GLE illustrated in FIG. 8, the load causedby the wiring resistance of the scanning signal lines GL is as follows.That is, the wiring resistance of the scanning signal lines GL increasesin proportion to a path distance from an end of the scanning signallines GL to the gate electrode GE of the pixel PX (see FIG. 4). Also, asillustrated in FIG. 7, the wiring resistance of the scanning signallines GL increases under an influence of the parasitic capacitance asthe number of times the scanning signal lines GL cross the transistorTr1 of each of the pixels and the video signal lines SL is increased.Accordingly, in order to improve display quality, it is preferred that adifference in time constant corresponding to each of the plurality ofpixels PX be reduced.

Accordingly, in this embodiment, the load given to the plurality ofpixels PX (see FIG. 8) is made even by adjusting the wiring resistanceof the enable line GWE supplying a potential as a scanning signal Gsi(see FIG. 6) to the scanning signal line GL via the driving circuit GDillustrated in FIG. 6. Specifically, as described with reference to FIG.2, the display device DSP1 includes the wiring layer (first wiringlayer) WL1, and the wiring layer (second wiring layer) WL2 made of amaterial having resistivity lower than that of the wiring layer WL1. Aconductor pattern formed in the wiring layer WL1 is made of, forexample, metal such as chrome (Cr), titanium (Ti), and molybdenum (Mo),or an alloy thereof. The conductor pattern formed in the wiring layerWL2 is made of a metal film having a multilayer structure, for example,in which aluminum (Al) is sandwiched with molybdenum (Mo), titanium(Ti), or the like. In this case, resistivity (specific resistance) ofthe wiring layer WL1 is higher than specific resistance of the wiringlayer WL2. As illustrated in FIG. 2, the scanning signal lines GL areformed in the wiring layer WL1. Then, the enable line (first potentialsupply line) GWE1 goes through the wiring layer WL1 and the wiring layerWL2 in a region overlapping with the extension portion EXT3.

Considering only from a viewpoint of reducing the wiring resistance ofthe enable line GWE1, it is preferred that the enable line GWE1 not gothrough the wiring layer WL1. For example, in a case where the enableline GWE1 goes through only the wiring layer WL2, it is possible toreduce the load that is given to the pixel PX caused by the wiringresistance of the enable line GWE1 to a substantially ignorable degree.However, in a case where a part of the enable line GWE1 goes through thewiring layer WL1, it is possible to adjust a value of the wiringresistance of the enable line GWE1 according to a wiring path distanceof the part going through the wiring layer WL1. For example, in theexample illustrated in FIG. 8, in a wiring path of the enable line GWE1from the control circuit CTC to the circuit block GBA1, the enable lineGWE1 goes through the wiring layer WL1 at a plurality of parts (a partindicated with a solid line extending in the X direction).

Here, a total value of the wiring path distance of the part goingthrough the wiring layer WL1, of the enable line GWE1 supplying thepotential to the scanning signal line GLA, for example, is longer thanthe wiring path distance of the part going through the wiring layer WL1,of the enable line GWE1 supplying the potential to the scanning signalline GLE. In this case, the wiring resistance of the enable line GWE1supplying the potential to the scanning signal line GLA is larger thanthe wiring resistance of the enable line GWE1 supplying the potential tothe scanning signal line GLE. Also, in a case where the part of theenable line GWE1 going through the wiring layer WL1, the wiringresistance of the enable line GWE1 is included in the load factor givento each of the pixel PXA and the pixel PXE. Then, with regard to thescanning signal Gsi for the pixel PXA and the pixel PXE, it is possibleto reduce the difference in time constant by comprehensively consideringinfluences of the wiring resistance of the scanning signal line GL, thewiring resistance of the enable wiring GWE1, and the parasiticcapacitance C1. In other words, it is possible to reduce an in-planedifference of the time constant of each of the plurality of pixels PXarranged in the display region DA. That is, according to thisembodiment, by adjusting the wiring resistance of the enable wiringGWE1, variation in in-plane distribution of the load caused by thewiring resistance of the scanning signal lines GL and by the parasiticcapacitance C1 is reduced. As a result, it is possible to improve thequality of an image displayed on the display device DSP1.

Also, the driving circuit GD1 includes the circuit block (first Acircuit block) GBA1, the circuit block (first B circuit block) GBB1, thecircuit block (first C circuit block) GBC1, and the circuit block (firstD circuit block) GBD1. In the example illustrated in FIG. 8, the circuitblock GBA1 and the circuit block GBB1 overlap with the extension portionEXT3, and the circuit block GBC1 and the circuit block GBD1 overlap withthe bent portion BEN1. The enable line GWE1 goes through the wiringlayer WL1 between the circuit block GBA1 and the circuit block GBB1 at adistance (first distance) D1. Also, the enable line GWE1 goes throughthe wiring layer WL1 between the circuit block GBC1 and the circuitblock GBD1 at a distance (first distance) D2. The distance D2 is shorterthan the distance D1.

In the example illustrated in FIG. 8, the enable line GWE1 goes throughthe wiring layer WL1 between the circuit block GDB1, which is at aterminal end of the driving circuit GD1, and the circuit block GBA1adjacent thereto at a distance D4. In the example illustrated in FIG. 8,the distance D4 is shorter than the distance D1. However, since a lengthof the distance D4 is determined according to a space of the extensionportion EXT3, the distance D4 may be the same as the distance D1 in somecases.

Also, the driving circuit GD2 includes a circuit block (second A circuitblock) GBA2 and a circuit block (second B circuit block) GBB2. In theexample illustrated in FIG. 8, the circuit block GBA2 and the circuitblock GBB2 overlap with the bent portion BEN2. The enable line GWE2 goesthrough the wiring layer WL1 between the circuit block GBA2 and thecircuit block GBB2 at a distance (third distance) D3. The distance D1 islonger than the distance D3.

Each of the plurality of scanning signal lines GL extends along the Xdirection. Accordingly, when, among the enable lines GWE1 and GWE2, apart formed in the wiring layer WL1 extends along the X direction, it iseasy to make resistance values of the plurality of signal transmissionpaths (wiring path distance including the enable line GWE and thescanning signal line GL) even. A length of the extension portion EXT3 inthe X direction is longer than a length of the bent portion BEN1 orlength of the bent portion BEN2 in the X direction. Thus, in the regionoverlapping with the extension portion EXT3, compared to a regionoverlapping with the bent portion BEN1 or BEN2, it is possible to make awiring length in the X direction longer. Thus, as illustrated in FIG. 8,in a case where the distance D1 is longer than the distance D2 or thedistance D3, it is easy to make the resistance values of the pluralityof signal transmission paths even.

Also, in the example illustrated in FIG. 8, in the region overlappingwith the bent portion BEN2, the enable line (second potential supplyline) GWE2 goes through the wiring layer WL1 and the wiring layer WL2.In this case, by adjusting the wiring resistance of the enable wiringGWE2, it is possible to reduce the variation in in-plane distribution ofthe load caused by the wiring resistance of the scanning signal lines GLand the parasitic capacitance C1. However, since the extension portionEXT3 has a larger area than the bent portion BEN2, it is possible tomake a distance at which the enable line GWE2 goes through the wiringlayer WL1 longer. Accordingly, an effect of preventing variation in timeconstant due to the part of the enable line going through the wiringlayer WL1 is relatively higher in the enable line GWE1. However, in acase where each of the enable line GWE1 and the enable line GWE2 goesthrough both of the wiring layer WL1 and the wiring layer WL2, theeffect of preventing variation in time constant is especially high.

Also, as in this embodiment, from a viewpoint of reducing an in-planedifference of the load given to the plurality of pixels PX, for a partconnected to the scanning signal line GL having the relatively lowwiring resistance, it may be preferred that the part of the enable lineGWE1 or GWE2 not go through the wiring layer WL1, in some cases. Forexample, in the example illustrated in FIG. 8, in a region overlappingwith the extension portion EXT1, the enable line GWE1 goes through thewiring layer WL2 and does not go through the wiring layer WL1. Also, ina region overlapping with the extension portion EXT2, the enable lineGWE2 goes through the wiring layer WL2 and does not go through thewiring layer WL1. A length of each of the plurality of scanning signallines GL connecting the extension portion EXT1 to the extension portionEXT2 is designed to be the same (although there may be a smalldifference due to processing accuracy and the like). The length of eachof the plurality of scanning signal lines GL connecting the extensionportion EXT1 to the extension portion EXT2 is the longest among theplurality of scanning signal lines GL provided in the display deviceDSP1. For example, like the scanning signal line GLE, the length of eachof the plurality of scanning signal lines GL having one end overlappingwith the extension portion EXT1 and the other end overlapping with theextension portion EXT2 is longer than the length of the scanning signalline GL (for example, the scanning signal line GLA) having one endoverlapping with the extension portion EXT3. That is, the wiringresistance of the scanning signal line GLE is larger than the wiringresistance of the scanning signal line GLA. Thus, in the regionsoverlapping with the extension portions EXT1 and EXT2, even when thewiring resistance of the path (enable lines GWE1 and GWE2) for supplyinga potential is increased, it is not possible to obtain an effect ofreducing the in-plane difference of the time constant. Also, when thewiring resistance of the enable lines GWE1 and GWE2 as a whole is large,the load given to each of the plurality of pixels PX becomes large.Thus, from a viewpoint of increasing an adjusting margin of the wiringresistance of the enable lines GWE1 and GWE2, it is preferred that theenable lines GWE1 and GWE2 not go through the wiring layer WL1 in theregion overlapping with the extension portion EXT1 and in the regionoverlapping with the extension portion EXT2.

Also, the driving circuit GD2 includes the circuit block (second Ccircuit block) GBC2 and the circuit block (second D circuit block) GBD2.The circuit block GBC1 and the circuit block GBC2 are connected to thesame scanning signal line GLC. Also, the circuit block GBD1 and thecircuit block GBD2 are connected to the same scanning signal line GLD.Here, the enable line GWE1 goes through the wiring layer WL1 and thewiring layer WL2 between the circuit block GBC1 and the circuit blockGBD1. Meanwhile, the enable line GWE2 goes through the wiring layer WL2and does not go through the wiring layer WL1, between the circuit blockGBC2 and the circuit block GBD2. In the example illustrated in FIG. 8,the circuit block GBC2 overlaps with the bent portion BEN2, and thecircuit block GBD2 overlaps with the extension portion EXT2. The circuitblock GBC2 is disposed in the vicinity of the extension portion EXT2 andis disposed on an extended line of an arrangement line of the pluralityof circuit blocks GDB2 disposed in a position to overlap the extensionportion EXT2. In this case, as long as the enable line GWE1 goes throughthe wiring layer WL1 and the wiring layer WL2 between the circuit blockGBC1 and the circuit block GBD1, it is possible to adjust the load givento the pixels PX even when the enable line GWE2 does not go through thewiring layer WL1.

Also, the part of the enable line GWE1 overlaps with the extensionportion EXT1. In the region overlapping with the extension portion EXT1,the enable line GWE1 goes through the wiring layer WL2 and does not gothrough the wiring layer WL1. Accordingly, for example, it is possibleto reduce the load given to the pixel PXE connected to the scanningsignal line GLE.

However, even in a case where the part of the enable line GWE1 goesthrough the wiring layer WL1 in the region overlapping with theextension portion EXT1 and even in a case where the part of the enableline GWE2 goes through the wiring layer WL1 in the region overlappingwith the extension portion EXT2, it is not possible to make the distanceat which the enable lines GWE1 and GWE2 go through the wiring layer WL1longer due to a limitation on space. Thus, as a modification of FIG. 8,in the region overlapping with the extension portion EXT1 and in theregion overlapping with the extension portion EXT2, the respective partsof the enable lines GWE1 and GWE2 may go through the wiring layer WL1.

Also, in this embodiment, a driving circuit is connected to either endof each of the plurality of scanning signal lines GL. In other words,each of the plurality of scanning signal lines GL is driven by theboth-side driving method. In this way, in a case where the plurality ofscanning signal lines GL are driven by the both-side driving method,when a part of the plurality of scanning signal lines GL is driven bythe one-side driving method, it may be a cause of making the in-planedistribution of the load given to the plurality of scanning signal linesGL uneven. That is, from a viewpoint of improving the image quality, itis preferred that all of the scanning signal lines GL be driven by theboth-side driving method.

Supposedly, when the planar shape of the display region DA is a squareor a rectangle, it is easy to make each length of the plurality ofscanning signal lines GL even and to make each length of the pluralityof video signal lines SL even. Accordingly, it is relatively easy to setthe value of the load given to each of the plurality of pixels PXarrayed so as to overlap with the display region DA, to be substantiallyconstant. However, as in this embodiment, in the display device DSP1having the display region DA of an irregular shape, the in-planedistribution of the value of the load given to each of the plurality ofpixels PX may easily become uneven.

Thus, in a case of the display device DSP1 according to this embodiment,as illustrated in FIG. 3, the driving circuit GD1 extends to thevicinity of the bent portion BEN2 (see FIG. 2) across a regionoverlapping with the bent portion BEN1 (see FIG. 1). In other words, inplan view, the bent portion BEN2 is located between a terminationportion of the driving circuit GD1 and a termination portion of thedriving circuit GD2. Accordingly, the driving circuits GD are connectedto both ends of the scanning signal line GL1 which is arrayed theclosest to the Y2 side in the Y direction among the plurality ofscanning signal lines GL. In other words, each of the plurality ofscanning signal lines GL including the scanning signal line GL1 isdriven by the both-side driving method. Accordingly, it is possible toprevent deterioration of image quality caused by a part of the pluralityof scanning signal lines GL being driven by the one-side driving method.

The above-described configuration may also be described in the followingby using clock lines GWC1 and GWC2 illustrated in FIG. 9. FIG. 9 is anenlarged plan view illustrating an exemplary layout of wirings supplyinga clock signal to the driving circuit in the same part as the displaydevice illustrated in FIG. 8. In FIG. 9, for easy understanding of acircuit layout of the driving circuits GD1 and GD2, among the pluralityof control wirings GW illustrated in FIG. 6, the clock line GWCtransmitting the clock signal is representatively illustrated.

As illustrated in FIG. 9, that is, the display device DSP1 includes theclock line (first clock line) GWC1 connecting the control circuit CTC tothe driving circuit GD1 and in which a clock signal (first clock signal)GCL1 (see FIG. 6) is supplied, and the clock line (second clock line)GWC2 connecting the control circuit CTC to the driving circuit GD1 andin which a clock signal (second clock signal) GCL2 (see FIG. 6) issupplied. Also, in plan view, the bent portion BEN1 overlaps with theclock line GWC1, and the bent portion BEN2 is located between atermination portion of the clock line GWC1 and a termination portion ofthe clock line GWC2. As illustrated in FIG. 9, the termination portionof the clock line GWC1 is located between the bent portion BEN1 and thebent portion BEN2. In the example illustrated in FIG. 9, the terminationportion of the clock line GWC2 overlaps with the bent portion BEN2 whilethe termination portion of the clock line GWC1 does not overlap with thebent portion BEN2. To one of oblique sides of the display device DSP1having a trapezoidal planar shape, or a side along the extension portionEXT3 illustrated in FIG. 9, it is possible to dispose the drivingcircuit GD1 along the oblique side. Accordingly, it is possible to applythe both-side driving method of the scanning signal line GL up to thetermination portion of the driving circuit GD1 and the terminationportion of the driving circuit GD2, in other words, to the terminationportion of the clock line GWC1 and the termination portion of the clockline GWC2.

Next, among the load factors given to each of the plurality of pixels PXillustrated in FIG. 7, a load caused by the parasitic capacitance C1(see FIG. 7) between the scanning signal line GL and the video signalline SL will be considered. FIG. 10 is an enlarged plan view of adisplay device that is a modification of FIG. 8. Also, FIG. 11 is anenlarged plan view illustrating a circuit layout around the circuitblock illustrated in FIG. 10. Also, FIG. 12 is an enlarged plan viewillustrating a modification of FIG. 11. In FIGS. 11 and 12, the scanningsignal lines GL are indicated with hatching in order to identify aboundary between a wiring portion (main wiring portion) GLPM and awiring portion (sub-wiring portion) GLPS of each of the scanning signallines GL. Although the wiring portion GLPM and the wiring portion GLPSare indicated with the hatching of different types, the wiring portionGLPM and the wiring portion GLPS are conductor patterns that are formedof the same conductive material to be continuous to the wiring layer WL1(see FIG. 2).

In a case where the shape of the display region DA is not a square or arectangle, some of the plurality of scanning signal lines GL differ fromothers in the number of the video signal lines SL crossed thereby. Forexample, in the example illustrated in FIG. 8, in plan view, the numberof the video signal lines SL crossed by the scanning signal line GLAwithin the display region DA is different from the number of the videosignal lines SL crossed by the scanning signal line GLE within thedisplay region DA. Specifically, the number of the video signal lines SLcrossed by the scanning signal line GLA is smaller than the number ofthe video signal lines SL crossed by the scanning signal line GLE withinthe display region DA. In other words, the number of the parasiticcapacitances C1 (see FIG. 7) connected to a signal transmission path fortransmitting the scanning signal Gsi (see FIG. 6) to the pixel PXEillustrated in FIG. 8 is larger than the number of the parasiticcapacitances C1 connected to a signal transmission path for transmittingthe scanning signal Gsi to the pixel PXA. Thus, when only the parasiticcapacitances C1 illustrated in FIG. 7 are simply considered, the loadgiven to the pixel PXE is larger than the load given to the pixel PXA.Then, in order to improve the display quality, it is preferred that thein-plane difference of the load given to each of the plurality of pixelsPX be reduced as described above.

Accordingly, in a display device DSP2 illustrated in FIG. 10, a part ofthe plurality of video signal lines SL is extended to the regionoverlapping with the extension portion EXT3 of the peripheral region SAacross the display region DA. Then, in the extension portion EXT3, thescanning signal lines GL and the video signal lines SL cross each other.In this case, the number of the video signal lines SL crossed by onescanning signal line GL (for example, the scanning signal line GLA)overlapping with the extension portion EXT3 becomes larger than that inthe display device DSP1 illustrated in FIG. 8. That is, among the loadsgiven to the pixel PLA connected to the scanning signal line GLA, theload corresponding to the parasitic capacitance C1 illustrated in FIG. 7increases. Accordingly, it is possible to reduce the in-plane differenceof the load given to each of the plurality of pixels PX.

Specifically, as illustrated in FIG. 11, in plan view, the scanningsignal line GLA includes the wiring portion (main wiring portion) GLPMlocated between the driving circuit (first driving circuit) GD1 and thedisplay region DA and within the display region DA, and the wiringportion (sub-wiring portion) GLPS connected to the wiring portion GLPMand located between the driving circuit GD1 and an outer edge of theperipheral region SA. In plan view, the wiring portion GLPS crosses thevideo signal lines SL. The wiring portion GLPS is on an extended line ofthe wiring portion GLPM and extends along the X direction. In theexample illustrated in FIG. 11, each of the plurality of scanning signallines GL includes the wiring portion GLPM and the wiring portion GLPS.Also, each of the plurality of video signal lines SL includes a wiringportion (main wiring portion) SLPM within the display region DA in planview and a wiring portion (sub-wiring portion) SLPS in the peripheralregion SA in plan view. Then, in the peripheral region SA, or morespecifically, in the region overlapping with the extension portion EXT3,the wiring portion GLPS of each of the scanning signal lines GL crossesthe wiring portion SIPS of each of the plurality of video signal linesSL.

In the peripheral region SA, the parasitic capacitance C1 (see FIG. 7)is given to a part where the scanning signal line GLA crosses each ofthe plurality of video signal lines SL. Each of the parasiticcapacitances C1 at a plurality of crossing parts is included in the loadgiven to the pixel PXA (see FIG. 10) connected to the scanning signalline GLA. As a result, it is possible to reduce a difference between theload given to the pixel PXE and the load given to the pixel PXAillustrated in FIG. 10.

Also, in the example illustrated in FIG. 10, the plurality of scanningsignal lines GL including the scanning signal line GLA cross the videosignal lines SL in the region overlapping with the bent portion BEN2. Inthis case, it is possible to further increase the number of the videosignal lines SL crossed by the scanning signal line GLA in theperipheral region. However, on an extended line of the scanning signalline GLA, a length of the region overlapping with the extension portionEXT3 is longer than a length of the region overlapping with the bentportion BEN2. Accordingly, the number of the video signal lines SLcrossed by the scanning signal line GLA is larger in the regionoverlapping with the extension portion EXT3 than in the regionoverlapping with the bent portion BEN2.

Meanwhile, as in the display device DSP2, in a case where the wiringportion GLPS of the scanning signal lines GL and the wiring portion SLPSof the video signal lines SL are disposed in the peripheral region SA,depending on a layout of the control wirings GW (see FIG. 6) disposed inthe peripheral region SA, there may also be a case in which the controlwiring GW crosses the scanning signal line GL or the control wiring GWcrosses the video signal line SL. However, it is preferred that neitherthe scanning signal line GL nor the video signal line SE cross thecontrol wiring GW in plan view. For example, in the example illustratedin FIG. 11, the wiring portion GLPS of the scanning signal lines GL doesnot cross the enable line GWE1 in plan view. Also, the wiring portionSLPS of the video signal line SL does not cross the enable line GWE1 inplan view. Although not illustrated in FIG. 11, it is preferred thateach of the clock line GWC and the start pulse line GWS illustrated inFIG. 6 not cross the scanning signal line GL and the video signal lineSE in the peripheral region SA.

Also, as illustrated in FIG. 10, some of the plurality of scanningsignal lines GE do not have the wiring portion GLPS (see FIG. 11). Forexample, the scanning signal line GLE illustrated in FIG. 10 does nothave the wiring portion GLPS. In plan view, the number of the videosignal lines SL crossed by the scanning signal line GLA within thedisplay region DA is smaller than the number of the video signal linesSL crossed by the scanning signal line GLE. In the case of the displaydevice DSP2, among the plurality of scanning signal lines GL, the wiringportion GLPS is selectively provided to the scanning signal line GL thatcrosses the relatively small number of the video signal lines SL. Inparticular, the scanning signal line GLE has one end overlapping withthe extension portion EXT1 and the other end overlapping with theextension portion EXT2. Accordingly, the number of the video signallines SL crossed by the scanning signal line GLE within the displayregion GA is larger than the number thereof crossed by another of thescanning signal lines GL. From a viewpoint of reducing the in-planedifference of the load given to the plurality of pixels PX, it ispreferred that the wiring portion GIPS not be provided to the scanningsignal line GL having the maximum number of the video signal lines SLcrossed thereby within the display region DA, like the scanning signalline GLE.

The display device DSP2 illustrated in FIGS. 10 and 11 is similar to thedisplay device DSP1 illustrated in FIG. 8 except that the video signallines SL cross the scanning signal lines in the peripheral region SA.Accordingly, regarding a part common to the display device DSP1 and thedisplay device DSP2, a repeated description thereof is omitted.

Also, as in a display device DSP3 illustrated in FIG. 12, in a casewhere one scanning signal line GL crosses one video signal line SL atmultiple places in the peripheral region SA, it is possible to furtherincrease the number of the parasitic capacitances C1 given to the onescanning signal line GL. In the display device DSP3, a shape of thewiring portion GLPS is different from that in the display device DSP2illustrated in FIG. 11. In the display device DSP3, the wiring portionGLPS of the scanning signal lines GL (including at least the scanningsignal line GLA) includes a wiring portion (first wiring portion) GLP1connected to the wiring portion GLPM, and a wiring portion (secondwiring portion) GLP2 connected to the wiring portion GLPS and extendingin a position different from the wiring portion GLP1. The wiring portionGLP1 is on the extended line of the wiring portion GLPM and extendsalong the X direction. One end of the wiring portion GLP1 is connectedto the wiring portion GLPM. The other end of the wiring portion GLP1 isconnected to the wiring portion GLP2 via a wiring portion GLPJ extendingalong the Y direction. Also, the wiring portion GLP2 is not on theextended line of the wiring portion GLPM and extends along the Xdirection. Each of the wiring portion GLP1 and the wiring portion GLP2crosses the plurality of video signal lines SL in the peripheral regionSA (more specifically, in the region overlapping with the extensionportion EXT3). In other words, at least a part of the plurality of videosignal lines SL illustrated in FIG. 12 crosses the wiring portion GLPSat multiple places. In the exemplary scanning signal line GLAillustrated in FIG. 12, each of the six video signal lines SL crossesthe wiring portion GLP1 and the wiring portion GLP2 of the wiringportion GLPS.

In the display device DSP3, the number of the video signal lines SLcrossed by the scanning signal line GLA in the peripheral region SA isthe same as the number thereof in the display device DSP2 illustrated inFIG. 11. However, the scanning signal line GLA crosses the video signallines SL at more places in the display device DSP3 than in the displaydevice DSP2. In the example illustrated in FIG. 12, the scanning signalline GLA crosses each of the plurality of video signal lines SL at twoplaces. In this case, compared to the display device DSP2, it ispossible to increase the number of the parasitic capacitances C1 (seeFIG. 7) given to the scanning signal line GLA in the display deviceDSP3. Note that, in FIG. 12, as an example in which one scanning signalline GL crosses one video signal line SL at multiple places in theperipheral region SA, there is exemplified an aspect in which crossingoccurs at two places; however, the “multiple places” may also be threeor more places.

Also, in the example illustrated in FIG. 12, a length (length in the Xdirection) of the wiring portion GLP2 is shorter than a length (lengthin the X direction) of the wiring portion GLP1. Accordingly, some of theplurality of video signal lines SL crossing the wiring portion GLP1 maynot cross the wiring portion GLP2. In the exemplary scanning signallines GLA illustrated in FIG. 12, each of the two video signal lines SLcrosses the wiring portion GLP1 and does not cross the wiring portionGLP2. According to this embodiment, it is possible to mitigate adifference in the wiring resistance between the scanning signal linesGL.

The display device DSP3 illustrated in FIG. 12 is similar to the displaydevice DSP2 illustrated in FIG. 11 except for the difference describedabove. For example, similar to the display device DSP2 illustrated inFIG. 10, also in the display device DSP3, a part of the plurality ofscanning signal lines GL (for example, the scanning signal line GLE)does not have the wiring portion GLPS. Regarding a part common to thedisplay device DSPS and the display device DSP2, a repeated descriptionthereof is omitted.

Next, among the load factors given to each of the plurality of pixels PXillustrated in FIG. 7, a load caused by the parasitic capacitance C4,which is a parasitic capacitance between the scanning signal line GL andthe common electrode CE, will be considered. FIG. 13 is an enlarged planview of a display device that is another modification of FIG. 10. Also,FIG. 14 is an enlarged plan view illustrating a circuit layout around acircuit block illustrated in FIG. 13. FIG. 15 is an enlarged plan viewillustrating a circuit layout around a circuit block that is differentfrom the circuit block illustrated in FIG. 14 among the plurality ofcircuit blocks illustrated in FIG. 13. In FIGS. 13 to 15, a regionoverlapping with the common electrode CE is indicated with a dotpattern. Note that a difference between a display device DSP4 and thedisplay device DSP10 illustrated in FIG. 10 will be mainly described,and a repeated description is omitted hereinafter.

In a case where the shape of the display region DA is neither a squarenor a rectangle, some of the plurality of scanning signal lines GLdiffer from others in length of overlapping with the common electrodeCE. For example, in the example illustrated in FIG. 13, in plan view, alength at which the scanning signal line GLA overlaps with the commonelectrode CE is shorter than a length at which the scanning signal lineGLE overlaps with the common electrode CE. In other words, the number ofthe parasitic capacitances C4 (see FIG. 7) connected to a signaltransmission path for transmitting the scanning signal Gsi (see FIG. 6)to the pixel PXE illustrated in FIG. 13 is larger than the number of theparasitic capacitances C4 connected to a signal transmission path fortransmitting the scanning signal Gsi to the pixel PXA. Thus, when onlythe parasitic capacitance C4 illustrated in FIG. 7 is simply considered,the load given to the pixel PXE is larger than the load given to thepixel PXA. Then, in order to improve the display quality, it ispreferred that the in-plane difference of the load given to each of theplurality of pixels PX be reduced as described above.

In the display device DSP4 illustrated in FIGS. 13 to 15, a part of thecommon electrode CE is in the peripheral region SA, and the scanningsignal line GL and the common electrode CE overlap with each other inthe peripheral region SA. For example, in a part illustrated in FIG. 14,in the region overlapping with the extension portion EXT3 in theperipheral region SA, the wiring portion GLPS of the scanning signalline GL overlaps with the common electrode CE. In this case, a length atwhich the scanning signal line GL (for example, the scanning signal lineGLA) overlaps with the common electrode CE becomes longer than that inthe display device DSP1 (see FIG. 8) and that in the display device DSP2(see FIG. 10). That is, among the loads given to the pixel PXA connectedto the scanning signal line GLA, the load corresponding to the parasiticcapacitance C4 illustrated in FIG. 7 increases. Accordingly, thein-plane difference of the load given to each of the plurality of pixelsPX can be reduced.

Also, in the display device DSP4, a length at which the wiring portionGLPS of the scanning signal line GL overlaps with the common electrodeCE is not fixed. The length at which the wiring portion GLPS of thescanning signal line GL overlaps with the common electrode CE isdifferent depending on the number of the video signal lines SL crossedby the scanning signal line GL. The larger the number of the videosignal lines SL crossed thereby, the larger the load caused by theparasitic capacitance C1 illustrated in FIG. 7 becomes, whereby the loadcaused by the parasitic capacitance C4 may be small. Accordingly, thelarger the number of the video signal lines SL crossed by the scanningsignal line GL is, the shorter a distance at which the scanning signalline GL overlaps with the common electrode CE is. In contrast, in a casewhere the number of the video signal lines SL crossed thereby is small,the load caused by the parasitic capacitance C1 illustrated in FIG. 7 issmall, whereby it is necessary to increase the overall load byincreasing the load caused by the parasitic capacitance C4. Accordingly,it is preferred that the distance at which the scanning signal line GLoverlaps with the common electrode CE be long as the number of the videosignal lines SL crossed thereby is small.

As illustrated in FIG. 15, for example, the wiring portion GLPS of thescanning signal line GL overlaps with the common electrode CE in theregion overlapping with the bent portion BEN1. Comparing the scanningsignal line GLA illustrated in FIG. 14 with the scanning signal line GLDillustrated in FIG. 15, in plan view, the number of the video signallines SL crossed by the scanning signal line GLA within the displayregion DA is smaller than the number of the video signal lines SLcrossed by the scanning signal line GLD. In this case, in the peripheralregion SA, a length at which the wiring portion GLPS of the scanningsignal line GLA overlaps with the common electrode CE is longer than alength at which the wiring portion GLPS of the scanning signal line GLDoverlaps with the common electrode CE. Also, similar to the displaydevice DSP2 described with reference to FIG. 10, the scanning signalline GL crossing the maximum number of the video signal lines SL withinthe display region DA, like the scanning signal line GLE (see FIG. 13),for example, does not have the wiring portion GLPS. In this way, in acase where the length at which the wiring portion GLPS of the scanningsignal line GL overlaps with the common electrode CE is differentdepending on the number of the video signal lines SL crossed by thescanning signal line GL, among the loads given to each of the pluralityof pixels PX, it is possible to reduce the in-plane difference of theload caused by the parasitic capacitance C4 illustrated in FIG. 7.

It is also possible to use the technique described in the display deviceDSP4 illustrated in FIGS. 13 to 15 and the technique described in thedisplay device DSP3 illustrated in FIG. 12 in combination. FIG. 16 is anenlarged plan view illustrating a circuit layout around a circuit blockof a display device that is a modification of FIGS. 12 and 14. In adisplay device DSP5 illustrated in FIG. 16, the wiring portion GLPS ofthe scanning signal line GL (including at least the scanning signal lineGLA) includes the wiring portion (first wiring portion) GLP1 connectedto the wiring portion GLPM, and the wiring portion (second wiringportion) GLP2 connected to the wiring portion GLPS and extending in aposition different from the wiring portion GLP1. The wiring portion GLP1is on the extended line of the wiring portion GLPM and extends along theX direction. One end of the wiring portion GLP1 is connected to thewiring portion GLPM. The other end of the wiring portion GLP1 isconnected to the wiring portion GLP2 via the wiring portion GLPJextending along the Y direction. Also, the wiring portion GLP2 is not onthe extended line of the wiring portion GLPM and extends along the Xdirection. Each of the wiring portion GLP1 and the wiring portion GLP2overlaps with the common electrode CE in the peripheral region SA (morespecifically, in the region overlapping with the extension portionEXT3). In the display device DSP5, a distance at which the scanningsignal line GLA overlaps with the common electrode CE is much longerthan that in the display device DSP4 illustrated in FIG. 14.

Next, a circuit layout in the peripheral region SA on the Y1 sideopposite to the Y2 side in the Y direction illustrated in FIG. 1 will bedescribed. To the other of the oblique sides of the display device DSP1having the trapezoidal planar shape, or a side along the extensionportion EXT4 (see FIG. 1), the switching circuit SWS is disposed, andthe plurality of video signal lines SL extend toward the display regionDA. Accordingly, it is difficult to dispose the driving circuit GD1 orthe driving circuit GD2 along the extension portion EXT4. Thus, at aside on the Y1 side in the Y direction illustrated in FIG. 3, a circuitlayout different from that at a side on the Y2 side is applied.

FIG. 17 is an enlarged plan view illustrating details of a circuitconfiguration of a lower side of the display device illustrated in FIG.3. Also, FIG. 18 is an enlarged plan view illustrating an exemplarylayout of a common electrode on a plane illustrated in FIG. 17. Asillustrated in FIG. 17, the display device DSP1 is provided with theswitching circuit (selection circuit) SWS between the display region DAand the driver chip DRC1 in which the control circuit CTC (see FIG. 6)is formed. Also, in plan view, there is neither the driving circuit GD1nor the driving circuit GD2 between the switching circuit SWS and thedisplay region DA. In this case, each of the plurality of video signallines SL has no bent portion in the middle and extends linearly from theswitch circuit SWS along the Y direction. The total number of the videosignal lines SL is larger than the total number of the scanning signallines GL. Accordingly, it is preferred that each of the plurality ofvideo signal lines SL be not curved but be linearly extended.

Meanwhile, some of the plurality of scanning signal lines GL have thebent portion, like a scanning signal line GLn1 and a scanning signalline GLn2 illustrated in FIG. 17, for example. Specifically, thescanning signal line GLn1 and the scanning signal line GLn2 goingthrough a region between the display region DA and the switch circuitSWS each have the bent portion in the peripheral region SA. A part ofeach of the scanning signal line GLn1 and the scanning signal line GLn2extends in the region between the display region DA and the switchcircuit SWS (in other words, a region between the display region DA andthe control circuit CTC of the driver chip DRC1). However, each of theplurality of scanning signal lines GL extends along the X directionwithin the display region DA (in other words, within a sectionoverlapping with the display region DA). Further, within the displayregion DA, each of the plurality of scanning signal lines GL is arrayedat an equal interval.

In a case where the both-side driving method is applied to each of theplurality of scanning signal lines GL, the number of the circuit blocksGDB1 constituting the driving circuit GD1 is the same as the number ofthe circuit blocks GDB2 constituting the driving circuit GD2. However,since the extension portion EXT1 and the extension portion EXT2 havedifferent lengths as described above, respective spaces in which thecircuit blocks GDB1 and GDB2 are disposed are different from each other.That is, as described above, the extension portion EXT2 is longer thanthe extension portion EXT1 in the Y direction. In this case, in a regionoverlapping with the extension portion EXT2, it is possible to secure alarger space in which the plurality of circuit blocks GDB2 constitutingthe driving circuit GD2 are disposed. Accordingly, the plurality ofcircuit blocks GDB2 are linearly arrayed along the Y direction. In otherwords, it is easy to dispose the plurality of circuit blocks GDB2constituting the driving circuit GD2 by avoiding a space between theswitching circuit SWS and the display region DA.

Meanwhile, a region overlapping with the extension portion EXT1 is aspace in which the plurality of circuit blocks GDB1 constituting thedriving circuit GD1 are disposed, and an area thereof is smaller than anarea of the region overlapping with the extension portion EXT2. As aresult, the plurality of circuit blocks GDB1 constituting the drivingcircuit GD1 are disposed not only in the region overlapping with theextension portion EXT1 but also in a region overlapping with the bentportion BEN3. The circuit blocks GDB1 overlapping with the bent portionBEN3 are disposed at a smaller pitch than the circuit blocks GDB2overlapping with the extension portion EXT2. Accordingly, in the regionon the Y2 side, the circuit block GDB1 and the circuit block GDB2, whichare disposed in mutually different positions in the Y direction, may beconnected via one scanning signal line GL. For example, each of thescanning signal line GLn1 and the scanning signal line GLn2 illustratedin FIG. 17 has one end connected to the circuit block GDB1 and the otherend connected to the circuit block GDB2. Then, in the Y direction, thepositions of the circuit block GDB1 and the circuit block GDB2 aredifferent from each other.

Also, as illustrated in FIG. 17, within the display region DA, thenumber of the plurality of video signal lines SL crossed by the scanningsignal line GLn1 is different from the number of the plurality of videosignal lines SL crossed by the scanning signal line GLn2. In the exampleillustrated in FIG. 17, in plan view, within the display region DA, thenumber of the plurality of video signal lines SL crossed by the scanningsignal line GLn1 is smaller than the number of the plurality of videosignal lines SL crossed by the scanning signal line GLn2. The pixel PXillustrated in FIG. 7 is provided to each crossing between the scanningsignal line GL and the video signal line SL, whereby a relation betweenthe scanning signal line GLn1 and the scanning signal line GLn2illustrated in FIG. 17 may be expressed as follows. That is, the numberof the pixels PX connected to the scanning signal line GLn1 is smallerthan the number of the pixels PX connected to the scanning signal lineGLn2. Also, since each pixel PX includes the transistor (pixeltransistor) Tr1, it may also be expressed as follows. The number of thetransistors Tr1 connected to the scanning signal line GLn1 is smallerthan the number of the transistors Tr1 connected to the scanning signalline GLn2.

In the example illustrated in FIG. 17, in plan view, the number of theplurality of video signal lines SL crossed by the scanning signal lineGLn1 is the same as the number of the plurality of video signal lines SLcrossed by the scanning signal line GLn2. Accordingly, among the loadfactors given to each of the plurality of pixels PX illustrated in FIG.7, the load caused by the parasitic capacitance C1 is made even.However, there is a possibility that the load caused by the parasiticcapacitance C3 may have a large in-plane difference due to the followingreason.

That is, the parasitic capacitance C3 changes with the number of thetransistors Tr1 connected to the scanning signal lines GL. Asillustrated in FIG. 17, in a case where the number of the transistorsTr1 (see FIG. 7) connected to the scanning signal line GLn1 is smallerthan the number of the transistors Tr1 connected to the scanning signalline GLn2, the load given to the scanning signal line GLn1 becomesrelatively small. As a method for reducing the in-plane difference ofthe load caused by the parasitic capacitance C3, there is a method forreducing a difference in the number of the transistors Tr1 connected tothe plurality of scanning signal lines GL by disposing a transistor (atransistor of a dummy pixel and the like) having a similar structure asthat of the transistor Tr1 in the peripheral region SA. However, asillustrated in FIG. 17, in the region between the display region DA andthe switch circuit SWS, a part of the scanning signal lines GL are leadout toward the Y1 side of a connecting position with the circuit blockGDB1 and are arrayed at an arrangement pitch, which is narrower thanthat in another region, along the outer edge portion (a side of an outerperiphery) of the display region DA. Also, since the arrangement pitchof the plurality of circuit blocks GDB1 is narrower in this region,there is a region in which an arrangement density of the scanning signallines GE is locally high. In FIG. 17, in the region between the displayregion DA and the switch circuit SWS, there are a part in which theplurality of scanning signal lines GL orthogonally cross the pluralityof video signal lines SL in plan view, and a part in which the pluralityof scanning signal lines GL cross the plurality of video signal lines SEat an angle other than the right angle. Then, in the part in which theplurality of scanning signal lines GL cross the plurality of videosignal lines SL at an angle other than the right angle, the arrangementdensity of the scanning signal lines GL is relatively high. In this way,it is difficult to dispose the transistor Tr1 in the region where thearrangement density of the scanning signal lines GL is high.

Thus, to the scanning signal lines GL going through the region betweenthe display region DA and the switch circuit SWS, it is preferred thatvariation of the load caused by the parasitic capacitance C3 becompensated by another load. For example, as illustrated in FIG. 18, alength at which the scanning signal line GLn1 overlaps with the commonelectrode CE is longer than a length at which the scanning signal lineGLn2 overlaps with the common electrode CE. Accordingly, considering theparasitic capacitance C4 (see FIG. 7), the load caused by the parasiticcapacitance C4 given to the scanning signal line GLn1 is larger than theload caused by the parasitic capacitance C4 given to the scanning signalline GLn2. In this case, it is possible to reduce variation of the loadas a whole by compensating for the variation of the load caused by theparasitic capacitance C3 by the load caused by the parasitic capacitanceC4.

Also, as illustrated in FIGS. 17 and 18, the scanning signal line GLn1is disposed closer to the switch circuit SWS, or in other words, closerto the control circuit CTC of the driver chip DRC1, than the scanningsignal line GLn2. Also, a length of the scanning signal line GLn1 islonger than a length of the scanning signal line GLn2. Accordingly,considering the load caused by the wiring resistance of the scanningsignal lines GL, a load caused by the wiring resistance of the scanningsignal line GLn1 is larger than a load caused by the wiring resistanceof the scanning signal line GLn2. In this case, it is possible to reducethe variation of the load as a whole by compensating for the variationof the load caused by the parasitic capacitance C3 by the load caused bythe wiring resistance.

Next, among the load factors given to each of the plurality of pixels PXillustrated in FIG. 7, a load caused by the parasitic capacitance C2between the video signal line SL and the transistor Tr1 will beconsidered. Capacitance caused by the parasitic capacitance C2illustrated in FIG. 7 changes with the number of the transistors Tr1connected to the video signal line SL. Accordingly, in a case where thenumber of the transistors Tr1 connected to each of the plurality ofvideo signal lines SL is different from each other, there is variationof the load caused by the parasitic capacitance C2 given to each of theplurality of video signal lines SL. Also, as illustrated in FIG. 3, eachof the plurality of video signal lines SL extends in the Y direction,and the plurality of video signal lines SL differ from each other inlength of overlapping with the display region DA. For example, in theexample illustrated in FIG. 3, a length at which a video signal line SLmbeing closer to the X2 side than the video signal line SL1 overlaps withthe display region DA is longer than a length at which a video signalline SL1 overlaps with the display region DA. Also, in the exampleillustrated in FIG. 17, the display device DSP1 includes a video signalline (first video signal line) SLd1 and a video signal line (secondvideo signal line) SLd2. A length at which The video signal line SLd2overlaps with the display region DA is longer than a length at which thevideo signal line SLd1 overlaps with the display region DA. In thiscase, in plan view, the number of the transistors Tr1 (see FIG. 7)connected to the video signal line SLd1 is smaller than the number ofthe transistors Tr1 connected to the video signal line SLd2.Accordingly, the load caused by the parasitic capacitance C2 given tothe video signal line SLd1 is smaller than the load caused by theparasitic capacitance C2 given to the video signal line SLd2.

The peripheral region SA, which is located between the display region DAand the switch circuit SWS illustrated in FIG. 18, includes a regionoverlapping with the common electrode CE and a region not overlappingwith the common electrode CE. At least the video signal line SLd2 has apart not overlapping with the common electrode CE in the peripheralregion SA. In the peripheral region SA, a length at which the videosignal line SLd1 overlaps with the common electrode CE is longer than alength at which the video signal line SLd2 overlaps with the commonelectrode CE. Here, among the load factors given to each of theplurality of pixels PX illustrated in FIG. 7, the load caused by theparasitic capacitance C5 between the video signal line SL and the commonelectrode CE increases in proportion to the length at which the videosignal lines SL overlaps with the common electrode CE. Accordingly, aload caused by the parasitic capacitance C5 given to the video signalline SLd1 in the peripheral region SA is larger than a load caused bythe parasitic capacitance C5 given to the video signal line SLd2.Accordingly, it is possible to reduce the variation of the load as awhole by compensating for the variation of the load caused by theparasitic capacitance C2 by the load caused by the parasitic capacitanceC5.

Note that the above description that “in the peripheral region SA, alength at which the video signal line SLd1 overlaps with the commonelectrode CE is longer than a length at which the video signal line SLd2overlaps with the common electrode CE” includes not only an aspect inwhich each of the video signal line SLd1 and the video signal line SLd2overlaps with the common electrode CE in the peripheral region SA, butalso an aspect in which the video signal line SLd2 does not overlap withthe common electrode CE in the peripheral region SA.

Also, in the example illustrated in FIG. 17, each of the plurality ofvideo signal lines SL has a different length from the switching circuitSWS to the display region DA. The plurality of video signal lines SLinclude a video signal line (third video signal line) SLd3 and a videosignal line (fourth video signal line) SLd4. In plan view, a length ofthe video signal line SLd4 from the switching circuit SWS to the displayregion DA is longer than a length of the video signal line SLd3 from theswitching circuit SWS to the display region DA. As illustrated in FIG.17, among the plurality of scanning signal lines GL, the scanning signalline GLn1 disposed in a position the closest to the switching circuitSWS crosses the video signal line SLd3 within the display region DA.Since the video signal line SLd3 does not need to cross the scanningsignal line GL outside the display region DA (that is, in the peripheralregion SA), it is possible to make the length to the switch circuit SWSrelatively short. In contrast, the scanning signal line GLn1 crosses thevideo signal line SLd4 outside the display region DA (more specifically,between the display region DA and the switching circuit SWS). When thelength of the video signal line SLd4 from the switch circuit SWS to thedisplay region DA is long, it is possible to cross the plurality ofscanning signal lines GL with the video signal line SLd4 in theperipheral region SA.

By allowing some of the plurality of scanning signal lines GL to crossthe video signal lines SLd4 outside the display region DA) in this way,it is possible to make the number of crossing between each of theplurality of video signal line SL and each of the plurality of scanningsignal lines GE even. As described with reference to FIG. 7, theparasitic capacitance C1 between the scanning signal line GE and thevideo signal line SL is one of the load factors given to the pixel PX.Thus, by making the number of crossing between each of the plurality ofvideo signal lines SL and each of the plurality of scanning signal linesGE even, it is possible to reduce variation in in-plane distribution ofthe load given to the pixel PX.

Also, in the example illustrated in FIG. 18, a length at which the videosignal line SLd3 overlaps with the common electrode CE is longer than alength at which the video signal line SLd4 overlaps with the commonelectrode CE. In contrast, in the peripheral region SA, the length atwhich the video signal line SLd4 overlaps with the common electrode CEis longer than the length at which the video signal line SLd3 overlapswith the common electrode CE. The video signal line SLd1 is closer tothe X1 side than the video signal line SLd3 and has a shorter overalllength. Accordingly, within the display region DA, the length at whichthe video signal line SLd3 overlaps with the common electrode CE islonger than the length at which the video signal line SLd4 overlaps withthe common electrode CE. In this case, there is variation of the loadcaused by the parasitic capacitance C5 described with reference to FIG.7. As illustrated in FIG. 18, in the peripheral region SA, in a casewhere the length at which the video signal line SLd4 overlaps with thecommon electrode CE longer than the length at which the video signalline SLd3 overlaps with the common electrode CE, it is possible toreduce the variation of the load caused by the parasitic capacitance C5.

In the foregoing, the technique found by the inventor of the presentapplication has been concretely described based on the embodiments byway of example. However, the present invention is not limited to theforegoing embodiments and various modifications and alterations can bemade within the scope of the present invention.

For example, in the above-described embodiment, a case of a liquidcrystal display device has been exemplified as an exemplary disclosure;however, as another exemplary application, it is possible to list allsorts of flat panel display devices such as an organic EL display deviceand another light emitting display device as well as an electronic paperdisplay device having an electrophoretic element and the like. Also, itis applicable to any size of display device, from a small-sized displaydevice to a large-sized display device, without any limitation inparticular.

For example, as one example of a display device having a display regionof an irregular shape other than a square or a rectangle, the displaydevice having the trapezoidal display region has been described. Theshape of the display region DA, however, may also be other than atrapezoid as well. For example, the shape of the display region DA mayalso be a parallelogram.

In the above-described embodiment, for example, as illustrated in FIG.3, there has been described the aspect in which both of ends of each ofthe plurality of scanning signal lines GL are connected to the drivingcircuit GD1 and the driving circuit GD2 and the display region DA as awhole is driven by the both-side driving method. However, as amodification, it is also possible to drive the display region DA as awhole by the one-side driving method. In this case, for example, nodriving circuit GD1 illustrated in FIG. 3 is disposed, and all of thescanning signal lines GL are driven by the driving circuit GD2 by theone-side driving method. It is also possible that each of the pluralityof scanning signal lines GL is connected to either one of the drivingcircuit GD1 and the driving circuit GD2 and not to the other.

For example, in each of the drawings such as FIG. 6 that illustrates arelation between the driving circuit GD and the scanning signal line GLconnected to the driving circuit GD, there has been also described anexample in which one scanning signal line GL is connected to each of thecircuit blocks GDB in which one switching circuit GSW is connected toone shift register circuit GSR. It is necessary that the switchingcircuit GSW correspond to the scanning signal line GL on a one-to-onebasis; however, as in a modification illustrated in FIG. 19, forexample, it is also possible to connect the plurality of switchingcircuits GSW to one shift register circuit GSR. FIG. 19 is a circuitblock diagram illustrating a modification of the circuit blockillustrated in FIG. 6. In the example illustrated in FIG. 19, fourswitching circuits GSW are connected to each of the plurality of shiftregister circuits GSR. A set of one shift register circuit GSR and fourswitching circuits GSW constitutes one circuit block. Also, to each ofthe plurality of switching circuits, one scanning signal line GE isconnected.

Also, in the modification illustrated in FIG. 19, each of the enableline GWE independent from each other is connected to each of theswitching circuits GSW included in one circuit block GDB. In this case,by combining a pulse signal supplied from the shift register circuit GSRwith a pulse signal supplied from the enable line GWE, it is possible tosequentially transmit the scanning signal Gsi (see FIG. 6) to each ofthe plurality of scanning signal lines GL. In the modificationillustrated in FIG. 19, compared to the example described with referenceto FIG. 6, it is possible to reduce the number of the shift registercircuits GSR. Also, on the assumption that the number of the scanningsignal lines GL is the same as that in the example illustrated in FIG.6, as illustrated in FIG. 19, a configuration in which each of theplurality of scanning signal lines GL is connected to any of theplurality of enable lines GWE independent from each other isadvantageous from the following point. That is, since the number of theswitching circuits GSW connected to the enable line GWE becomes small(¼) in the example of the drawing, it is possible to reduce a loadcapacity of the enable lines GWE.

Also, in the present specification, various aspects based on thetechnical idea thereof have been described by dividing the aspects intomultiple modifications, and a repeated description is omitted on acommon part of the multiple aspects (modifications). Accordingly, it isalso possible to apply two or more of the above-described multiplemodifications in combination.

Various modifications and alterations can be conceived by those skilledin the art within the spirit of the present invention, and it isunderstood that such modifications and alterations are also encompassedwithin the scope of the present invention.

For example, those skilled in the art can suitably modify theabove-described embodiment by addition, deletion, or design change ofcomponents, or by addition, omission, or condition change of steps. Suchmodifications are also encompassed within the scope of the presentinvention as long as they include the gist of the present invention.

The present invention is effective when applied to an input device and adisplay device provided with an input detection function.

1-20. (canceled)
 21. A display device comprising: a display region inwhich a plurality of pixels is arrayed; a peripheral region surroundingthe display region; a plurality of video signal lines extended in afirst direction; a plurality of scanning signal lines extended in asecond direction crossing the first direction; a first driving circuitand a second driving circuit supplying a scanning signal; a plurality offirst electrodes provided in the plurality of pixels; and a secondelectrode opposed to the plurality of first electrodes, wherein thefirst driving circuit includes a plurality of circuit blocks connectedvia a first line to each other, the plurality of scanning signal linesinclude a first scanning signal line and a second scanning signal line,in the display region, a number of the plurality of video signal linescrossed by the first scanning signal line is smaller than a number ofthe plurality of video signal lines crossed by the second scanningsignal line, one of the first scanning signal line or the secondscanning signal line includes a first portion located in the displayregion and a second portion located in the peripheral region, the secondelectrode covers the first portion and the second portion, and formedalong the first line, and an end of the second electrode is between thefirst line and the display region.
 22. The display device according toclaim 21, further comprising a driving chip provided in the peripheralregion, wherein the second scanning signal line is closer to the drivingchip than the first scanning signal line.
 23. The display deviceaccording to claim 22, wherein the first scanning signal line includesthe first portion and the second portion.
 24. The display deviceaccording to claim 23, wherein the second scanning signal line does nothave a portion located in the peripheral region.
 25. The display deviceaccording to claim 21, wherein the first line is an enable linetransmitting an enable signal.
 26. The display device according to claim21, wherein the second electrode does not cover the plurality of circuitblocks.
 27. The display device according to claim 21, wherein one of theplurality of circuit blocks connected to the first scanning signal lineis sandwiched by the second electrode in a plan view.
 28. A displaydevice comprising: a substrate including a display region and aperipheral region surrounding the display region; a plurality of videosignal lines provided on the substrate and extended in a firstdirection; a plurality of scanning signal lines provided on thesubstrate and extended in a second direction crossing the firstdirection; a scanning signal output circuit including a plurality ofcircuit blocks; a potential supply line located in the peripheral regionand connecting the plurality of circuit blocks to each other, aplurality of first electrodes provided in the display region; and asecond electrode opposed to the plurality of first electrodes, whereinthe substrate includes a first side extending along the first direction,a second side opposed to the first side, a third side extending alongthe second direction, and a fourth side opposed to the third side, thescanning signal output circuit is in the peripheral region, one of theplurality of circuit blocks at a corner between the first side and thethird side is located closer to the second side than the other of theplurality of circuit blocks along the first side, and the potentialsupply line is between the first side and the scanning signal outputcircuit and is located along the plurality of circuit blocks.
 29. Thedisplay device according to claim 28, wherein an end of the secondelectrode is between the potential supply line and the display region.30. The display device according to claim 28, further comprising adriving chip provided in the peripheral region, wherein the driving chipis provided along the fourth side.
 31. The display device according toclaim 28, wherein the second electrode does not cover the plurality ofcircuit blocks.